1. Technical Field
The present invention generally relates to a voltage-controlled oscillator and a voltage-controlled delay line, and more particularly, to a voltage-controlled oscillator or a voltage-controlled delay line using hybrid current-starved phase-interpolation.
2. Description of the Related Art
Voltage-controlled delay (VCD) elements are useful in many applications. VCDs are important blocks in delay-locked loops (DLL) which synchronize an internal clock with an incoming clock.
Referring to FIG. 1, a typical block diagram of a DLL 10 is shown, which has a phase detector (PD) 14, a loop filter (LPF) 16, and a voltage-controlled delay line (VCDL) 12. The phase detector 14 compares the timing difference between a reference clock edge φref and a clock edge from the VCDL 12, which is a delayed version of a clock input, φin. Phase detector 14 generates an error voltage for the VCDL 12 to adjust the phase shift φout. The phase detector 14 is usually accompanied by a charge pump (CP) in typical IC designs.
The loop filter 16 between the phase detector 14 and the VCDL 12 rejects high frequency noise. The feedback operation provides a control voltage Vctr by a feedback loop 17, which forces the internal clock edge φref to be aligned to the incoming clock edge φin.
Also, the VCD has been employed to build a ring-oscillator voltage-controlled oscillator (VCO) which is one important building block in phase-locked loop (PLL) design.
Referring to FIG. 2, a delay line in a phase locked loop 20 includes a ring-oscillator VCO 22 having a plurality of VCDs 12. A phase-and-frequency detector (PFD) 14 and loop filter 16 are employed to provide a control signal to VCO 18.
For digital clock generation, current-starved ring VCOs 22 shown in FIG. 3 have been primarily used in the monolithic PLLs since they provide wide tuning range and high integration. (See e.g., I. Young, et. Al, “A PLL clock generator with 5 to 110 MHz of lock range for microprocessors”, IEEE JSSC, November 1992).
Referring to FIG. 3, the oscillation frequency of the current-starved ring VCO 22 is directly related to the delay time of each delay element 12, resulting in high sensitivity to process, voltage, and temperature (PVT) variation. The nonlinear voltage-to-frequency transfer characteristic of the current-starved ring VCO 22 results in a highly variable VCO gain characteristic which is undesirable in PLL implementations.
The VCO 18 includes a Vref input to a replica cell 24. The VCO 18 includes transistors M1, M2, M3 and M4. M3 and M4 are controlled in accordance with the output of the replica cell 24. Vdd is the supply voltage, and Vctl is employed to control a variable current source 26 at the foot of the oscillator. VIN and VINB represent V input and V input bar signals, and VO and VOB represent V output and V output bar signals, respectively. M1 and M2 are controlled in accordance with VIN and VINB, respectively.
Referring to FIG. 4, another way of implementing VCD elements is using a phase-interpolation method. An example of a circuit 30 implementation for phase-interpolation is shown in FIG. 4 and described in J. Savoj and B. Razavi, “A 10-Gb/s CMOS clock and data recovery circuit with a half-rate linear phase detector”, IEEE, JSSC, May 2001.
Compared to a VCD using a current-starved approach, a VCD 32 using a phase-interpolation method offers reduced phase noise and more linear voltage-to-frequency characteristics. However, VCD 32 has less tuning range than the current-starved ring oscillator. For this reason, the current-starved method is still widely used in digital clock generation applications.